1. Technical Field
This disclosure generally relates to semiconductor devices and, more particularly, to semiconductor devices such as memory devices having an air gap defined between adjacent gate structures and methods of fabricating the same.
2. Description of the Related Art
Among semiconductor devices, non-volatile memory devices are commonly used in consumer electronic devices because information can be retained in the device even when no power is supplied. Advances in consumer electronics cause demand for ever higher density memory devices. Efforts to manufacture devices meeting this demand often involve scaling down the sizes of gate structures and minimizing the space between adjacent gate structures.
Unfortunately, these efforts often result in increased parasitic capacitance between adjacent structures in the memory cell regions. Such increases in parasitic capacitance reduce the speed of the memory devices. Also, variation in parasitic capacitance between gate structures causes a variation in the threshold voltage for each gate structure, thereby degrading the reliability of memory devices.
FIG. 1a is a circuit diagram of a typical NAND flash memory array, which is a popular type of non-volatile memory device. As shown in FIG. 1a, the NAND flash memory array includes a string select line SSL, a ground select line GSL, a common source line CSL, a plurality of word lines W/L#0-31, and a plurality of bit lines BL crossing across the other lines. FIG. 1b is a schematic plan view of a typical NAND flash memory array corresponding to FIG. 1a. In FIG. 1b, active regions 16 and bit line contacts 146 are illustrated together with floating gates 22. FIG. 1c is a cross-sectional view of a NAND flash memory structure of FIG. 1b taken along the wordline direction. In the wordline direction, a cell gate structure includes a control gate 24, an inter-gate dielectric layer 23, a floating gate 22, a tunnel oxide 21, and isolation regions 15 formed on a semiconductor substrate 10. FIG. 1d is a cross-sectional view of the NAND flash memory structure of FIG. 1b taken along the bitline direction. As shown in FIG. 1d, in the bitline direction a cell gate structure includes the control gate 24, the inter-gate dielectric layer 23, the floating gate 22, the tunnel oxide 21, and impurity regions 16 formed on the semiconductor substrate 10.
FIG. 2 is a perspective view of a portion of a NAND memory cell array. The capacitances between various portions of the memory cell array and the voltages on some of the floating gates are identified in FIG. 2. For example, Vfg is a voltage at a central floating gate and Vcg is a voltage at a central control gate. Further, V1 and V2 are voltages between adjacent floating gates in the x-direction; and V3 and V4 are voltages between adjacent floating gates in the y direction. Furthermore, V5 and V6 are voltages between . . . . In addition, C stands for parasitic overlap capacitance. Using the relationship Q=CV as applied to the structure in FIG. 2, Equation 1 and 2 are developed. Equation 1 describes the variation of the floating gate voltage (ΔVfg) in one of the NAND memory cells of FIG. 2 as a function of the surrounding capacitances and voltages.
                              Δ          ⁢                                          ⁢                      V            fg                          =                                            C              fgy                        ⁡                          (                                                Δ                  ⁢                                                                          ⁢                                      V                    3                                                  +                                  Δ                  ⁢                                                                          ⁢                                      V                    4                                                              )                                                          C              ono                        +                          C              tun                        +                          2              ⁢                                                          ⁢                              C                fgx                                      +                          2              ⁢                                                          ⁢                              C                fgy                                      +                          2              ⁢                                                          ⁢                              C                fgcg                                                                        (                  Equation          ⁢                                          ⁢          1                )            As shown in Equation 1, decreasing Cfgy, the capacitance between adjacent floating gates 22 in the bitline direction, results in a decrease in the variation of the floating gate voltage (ΔVfg). Therefore, a low Cfgy improves the threshold voltage distribution among the cell gates in the memory cell array.
Equation 2 describes the floating gate voltage (Vfg) of one of the memory cells of FIG. 2 as a function of the surrounding voltages and capacitances.
                              V          fg                =                                                                                                                        C                      ono                                        *                                          V                      cg                                                        +                                                            C                      fgx                                        ⁢                                          (                                                                        V                          1                                                +                                                  V                          2                                                                    )                                                        +                                                                                                                                                C                      fgy                                        ⁡                                          (                                                                        V                          3                                                +                                                  V                          4                                                                    )                                                        +                                                            C                      fgcg                                        ⁡                                          (                                                                        V                          5                                                +                                                  V                          6                                                                    )                                                                                                                              C              ono                        +                          C              tun                        +                          2              ⁢                                                          ⁢                              C                fgx                                      +                          2              ⁢                                                          ⁢                              C                fgy                                      +                          2              ⁢                                                          ⁢                              C                fgcg                                                                        (                  Equation          ⁢                                          ⁢          2                )            
As shown in Equation 2, decreasing Cfgy, results in an increase in Vfg. Consequently, the coupling ratio can be increased and the speed performance of the device can be improved.
From the analysis above, one method to improve device performance as device density is increased is to reduce the parasitic capacitance between adjacent floating gates. Typically, the spaces between adjacent floating gates are filled by an insulating layer whose dielectric constant is a primary factor in determining the capacitance between the adjacent floating gates. An insulating layer formed from a material having a higher dielectric constant will cause increased parasitic capacitance between adjacent gate structures. Consequently, it is desirable to form the dielectric layer from the lowest dielectric constant material possible.
Table 1 is a list of the approximate dielectric constants of several materials. Typical dielectric layers are formed from silicon oxide or silicon nitride materials. As shown in Table 1, these materials have dielectric constants of approximately 3.9 and 7.8, respectively, Air, on the other hand, has an approximate dielectric constant of 1.005. Consequently, a substantial reduction in the parasitic capacitance between adjacent gate structures can be achieved by replacing the silicon oxide or nitride dielectric material commonly used in semiconductor, e.g., memory structures with air. Further, it is desired to fill as much of the space between adjacent gates as possible with air, as opposed to another dielectric material, to minimize the parasitic capacitance.
TABLE 1MaterialDielectric ConstantVacuum1 (By definition)Air1.005Polyethylene2.25Paper3Silicon oxide3.9Silicon nitride7.8Rubber7Silicon11.68Methyl alcohol30Water80Barium Titanate1200
One approach to reduce parasitic capacitance between adjacent gate structures is disclosed in U.S. Published Patent Application No. 20050023597 to Kutsukake et al. (hereinafter referred to as “Kutsukake”). In Kutsukake, air gaps are formed between gate structures simultaneously with gate sidewall spacers due to the conformal dielectric layer deposition process. Another approach is disclosed in Korean Published Patent Application 2002-0081926, in which air gaps are formed by depositing a thicker spacer layer on an upper portion of gate sidewalls than on a bottom portion thereof. One disadvantage of these approaches is that the area between adjacent gates is largely filled with an oxide dielectric layer with a relatively small air pocket. Therefore, the parasitic capacitance between the gates is not reduced as much as it would be if substantially the entire area were filled by an air gap or pocket.
This disclosure overcomes this and other disadvantages of previous approaches to minimizing the parasitic capacitance between adjacent gate structures.